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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asap/AvedilloQP05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/H%E2%88%9A%C2%A9ctor_Pettenghi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_M._Quintana>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maria_J._Avedillo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASAP.2005.43>
foaf:homepage <https://doi.org/10.1109/ASAP.2005.43>
dc:identifier DBLP conf/asap/AvedilloQP05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASAP.2005.43 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Logic Models Supporting the Design of MOBILE-based RTD Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/H%E2%88%9A%C2%A9ctor_Pettenghi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_M._Quintana>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maria_J._Avedillo>
swrc:pages 254-259 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asap/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/asap/AvedilloQP05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asap/AvedilloQP05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asap/asap2005.html#AvedilloQP05>
rdfs:seeAlso <https://doi.org/10.1109/ASAP.2005.43>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asap>
dc:title Logic Models Supporting the Design of MOBILE-based RTD Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document