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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asap/BednaraBTW00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%C4%BErgen_Teich>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcus_Bednara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Oliver_Beyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rolf_Wanka>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASAP.2000.862400>
foaf:homepage <https://doi.org/10.1109/ASAP.2000.862400>
dc:identifier DBLP conf/asap/BednaraBTW00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASAP.2000.862400 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%C4%BErgen_Teich>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcus_Bednara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Oliver_Beyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rolf_Wanka>
swrc:pages 299-308 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asap/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/asap/BednaraBTW00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asap/BednaraBTW00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asap/asap2000.html#BednaraBTW00>
rdfs:seeAlso <https://doi.org/10.1109/ASAP.2000.862400>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asap>
dc:subject Sorting, Systolic Arrays, Hardware/Software-Codesign (xsd:string)
dc:title Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document