Overcoming chip-to-chip delays and clock skews. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/asap/EvenL96>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Ami_Litman>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Guy_Even>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FASAP.1996.542815>
foaf:homepage	<https://doi.org/10.1109/ASAP.1996.542815>
dc:identifier	DBLP conf/asap/EvenL96 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FASAP.1996.542815 (xsd:string)
dcterms:issued	1996 (xsd:gYear)
rdfs:label	Overcoming chip-to-chip delays and clock skews. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Ami_Litman>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Guy_Even>
swrc:pages	199-208 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/asap/1996>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/asap/EvenL96/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/asap/EvenL96>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/asap/asap1996.html#EvenL96>
rdfs:seeAlso	<https://doi.org/10.1109/ASAP.1996.542815>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/asap>
dc:subject	systolic arrays; delays; logic design; chip-to-chip delays; clock skews; chip-to-chip interconnections; feasible clock period; systolic array; large systolic linear arrays; systolic two-dimensional arrays; logic duplication; retiming; functionality (xsd:string)
dc:title	Overcoming chip-to-chip delays and clock skews. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document