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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asap/FawcettW96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bradly_K._Fawcett>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Watson>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASAP.1996.542824>
foaf:homepage <https://doi.org/10.1109/ASAP.1996.542824>
dc:identifier DBLP conf/asap/FawcettW96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASAP.1996.542824 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Reconfigurable Processing With Field Programmable Gate Arrays. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bradly_K._Fawcett>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Watson>
swrc:pages 293-302 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asap/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/asap/FawcettW96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asap/FawcettW96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asap/asap1996.html#FawcettW96>
rdfs:seeAlso <https://doi.org/10.1109/ASAP.1996.542824>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asap>
dc:subject field programmable gate arrays; reconfigurable architectures; coprocessors; SRAM chips; reconfigurable processing; SRAM-based field programmable gate arrays; processors; coprocessors; internal architecture; interconnections; computationally-intensive tasks; programmable solution; XC6200 FPGA architecture; SRAM control store; on-chip memory capability (xsd:string)
dc:title Reconfigurable Processing With Field Programmable Gate Arrays. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document