A flexible VLSI architecture for variable block size segment matching with luminance correction.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/asap/KuhnWPS97
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1997
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A flexible VLSI architecture for variable block size segment matching with luminance correction.
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VLSI; flexible VLSI architecture; variable block size segment matching; luminance correction; segment matching VLSI architecture; evolving motion estimation algorithms; block matching algorithms; video coding standards; RAM; motion vectors; preprocessing unit; halfpel interpolation; pixel decimation; VHDL synthesis; CMOS technology
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A flexible VLSI architecture for variable block size segment matching with luminance correction.
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