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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asap/LeeSYM08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gary_F._Margrave>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lesley_Shannon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Matthew_J._Yedlin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASAP.2008.4580178>
foaf:homepage <https://doi.org/10.1109/ASAP.2008.4580178>
dc:identifier DBLP conf/asap/LeeSYM08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASAP.2008.4580178 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gary_F._Margrave>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lesley_Shannon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Matthew_J._Yedlin>
swrc:pages 197-202 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asap/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/asap/LeeSYM08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asap/LeeSYM08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asap/asap2008.html#LeeSYM08>
rdfs:seeAlso <https://doi.org/10.1109/ASAP.2008.4580178>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asap>
dc:title A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document