Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/asap/TavaresKMF08
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Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes.
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Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes.
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