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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asicon/HuaWWLL15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donghui_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiarui_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leiou_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Siliang_Hua>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yan_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASICON.2015.7517127>
foaf:homepage <https://doi.org/10.1109/ASICON.2015.7517127>
dc:identifier DBLP conf/asicon/HuaWWLL15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASICON.2015.7517127 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donghui_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiarui_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leiou_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Siliang_Hua>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yan_Liu>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asicon/2015>
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owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asicon/HuaWWLL15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asicon/asicon2015.html#HuaWWLL15>
rdfs:seeAlso <https://doi.org/10.1109/ASICON.2015.7517127>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asicon>
dc:title A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document