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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asicon/ZhangZSWZ23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hao_Zhou_0008>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jide_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaichuang_Shi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaixiang_Zhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lingli_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASICON58565.2023.10395964>
foaf:homepage <https://doi.org/10.1109/ASICON58565.2023.10395964>
dc:identifier DBLP conf/asicon/ZhangZSWZ23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASICON58565.2023.10395964 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hao_Zhou_0008>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jide_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaichuang_Shi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaixiang_Zhu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lingli_Wang>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asicon/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/asicon/ZhangZSWZ23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asicon/ZhangZSWZ23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asicon/asicon2023.html#ZhangZSWZ23>
rdfs:seeAlso <https://doi.org/10.1109/ASICON58565.2023.10395964>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asicon>
dc:title Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document