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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asicon/ZhaoLJYYZ23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Changhan_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chuan_Zhang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wuqiong_Zhao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaohu_You_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/You_You>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhenhao_Ji>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASICON58565.2023.10396119>
foaf:homepage <https://doi.org/10.1109/ASICON58565.2023.10396119>
dc:identifier DBLP conf/asicon/ZhaoLJYYZ23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASICON58565.2023.10396119 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Automatic Timing-Driven Top-Level Hardware Design for Digital Signal Processing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Changhan_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chuan_Zhang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wuqiong_Zhao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaohu_You_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/You_You>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhenhao_Ji>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asicon/2023>
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rdfs:seeAlso <https://doi.org/10.1109/ASICON58565.2023.10396119>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asicon>
dc:title Automatic Timing-Driven Top-Level Hardware Design for Digital Signal Processing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document