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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/BinhIT98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masaharu_Imai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nguyen-Ngoc_B%E2%88%9A%C2%A8nh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yoshinori_Takeuchi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.1998.669502>
foaf:homepage <https://doi.org/10.1109/ASPDAC.1998.669502>
dc:identifier DBLP conf/aspdac/BinhIT98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.1998.669502 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masaharu_Imai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nguyen-Ngoc_B%E2%88%9A%C2%A8nh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yoshinori_Takeuchi>
swrc:pages 367-372 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/BinhIT98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/BinhIT98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac98.html#BinhIT98>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.1998.669502>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document