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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/DabasDR07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaijeet_S._Roychowdhury>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ning_Dong_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Dabas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2007.358012>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2007.358012>
dc:identifier DBLP conf/aspdac/DabasDR07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2007.358012 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaijeet_S._Roychowdhury>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ning_Dong_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Dabas>
swrc:pages 361-366 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/DabasDR07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/DabasDR07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2007.html#DabasDR07>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2007.358012>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:subject gate delay modelling, accurate delay/timing macromodels, digital gates, latches, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, current-source models, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, XOR gates, full adder, sequential latch (xsd:string)
dc:title Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document