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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/HuangCTP10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chia-Ming_Chang_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Hsu_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Song-Bin_Pan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wen-Pin_Tu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2010.5419836>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2010.5419836>
dc:identifier DBLP conf/aspdac/HuangCTP10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2010.5419836 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chia-Ming_Chang_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Hsu_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Song-Bin_Pan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wen-Pin_Tu>
swrc:pages 480-485 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/HuangCTP10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/HuangCTP10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#HuangCTP10>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2010.5419836>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document