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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/HuangYYZ021>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Changhao_Yan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dian_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fan_Yang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiangli_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuan_Zeng_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3394885.3431543>
foaf:homepage <https://doi.org/10.1145/3394885.3431543>
dc:identifier DBLP conf/aspdac/HuangYYZ021 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3394885.3431543 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Changhao_Yan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dian_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fan_Yang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiangli_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuan_Zeng_0001>
swrc:pages 146-151 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/HuangYYZ021/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/HuangYYZ021>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2021.html#HuangYYZ021>
rdfs:seeAlso <https://doi.org/10.1145/3394885.3431543>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document