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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/IizukaIA04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kunihiro_Asada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Makoto_Ikeda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Iizuka>
foaf:homepage <http://dx.doi.org/doi.ieeecomputersociety.org%2F10.1109%2FASPDAC.2004.110>
foaf:homepage <https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.110>
dc:identifier DBLP conf/aspdac/IizukaIA04 (xsd:string)
dc:identifier DOI doi.ieeecomputersociety.org%2F10.1109%2FASPDAC.2004.110 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kunihiro_Asada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Makoto_Ikeda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Iizuka>
swrc:pages 149-154 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/IizukaIA04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/IizukaIA04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2004.html#IizukaIA04>
rdfs:seeAlso <https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.110>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document