Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/KaoL04
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Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
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Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
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