Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/LaiWR05>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jaijeet_S._Roychowdhury>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Xiaolue_Lai>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yayun_Wan>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1120725.1120913>
foaf:homepage	<https://doi.org/10.1145/1120725.1120913>
dc:identifier	DBLP conf/aspdac/LaiWR05 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1120725.1120913 (xsd:string)
dcterms:issued	2005 (xsd:gYear)
rdfs:label	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jaijeet_S._Roychowdhury>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Xiaolue_Lai>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Yayun_Wan>
swrc:pages	459-464 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2005>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/aspdac/LaiWR05/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/aspdac/LaiWR05>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#LaiWR05>
rdfs:seeAlso	<https://doi.org/10.1145/1120725.1120913>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document