Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/LeeYKKK05
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2005
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Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
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SoC, TLM, simulation acceleration, systemc, transaction-level modeling
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Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
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