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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/LiTCZ09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Duo_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gengsheng_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sheldon_X.-D._Tan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuan_Zeng_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2009.4796492>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2009.4796492>
dc:identifier DBLP conf/aspdac/LiTCZ09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2009.4796492 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Duo_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gengsheng_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sheldon_X.-D._Tan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuan_Zeng_0001>
swrc:pages 272-277 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/LiTCZ09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/LiTCZ09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2009.html#LiTCZ09>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2009.4796492>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document