Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/LinLH05
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Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
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Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
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