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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/RenFCZ12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Huailu_Ren>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaoyang_Zeng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xinhua_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yibo_Fan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2012.6165065>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2012.6165065>
dc:identifier DBLP conf/aspdac/RenFCZ12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2012.6165065 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k√ó2k H.264/AVC video encoder. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Huailu_Ren>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaoyang_Zeng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xinhua_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yibo_Fan>
swrc:pages 801-806 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2012>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/RenFCZ12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/RenFCZ12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2012.html#RenFCZ12>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2012.6165065>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k√ó2k H.264/AVC video encoder. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document