A Graph Reduction Approach to Symbolic Circuit Analysis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/ShiCS07
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/ShiCS07
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/C.-J._Richard_Shi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Guoyong_Shi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Weiwei_Chen
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2007.357985
>
foaf:
homepage
<
https://doi.org/10.1109/ASPDAC.2007.357985
>
dc:
identifier
DBLP conf/aspdac/ShiCS07
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FASPDAC.2007.357985
(xsd:string)
dcterms:
issued
2007
(xsd:gYear)
rdfs:
label
A Graph Reduction Approach to Symbolic Circuit Analysis.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/C.-J._Richard_Shi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Guoyong_Shi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Weiwei_Chen
>
swrc:
pages
197-202
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2007
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/aspdac/ShiCS07/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/aspdac/ShiCS07
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/aspdac/aspdac2007.html#ShiCS07
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ASPDAC.2007.357985
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/aspdac
>
dc:
subject
symbolic analog circuit simulator, graph reduction, symbolic circuit analysis, binary decision diagram, recursive sign determination algorithm
(xsd:string)
dc:
title
A Graph Reduction Approach to Symbolic Circuit Analysis.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document