Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18¬Ķm CMOS process.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/ShinmyoHO05
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Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18¬Ķm CMOS process.
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Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18¬Ķm CMOS process.
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