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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/SongKWLH22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chien-Nan_Jimmy_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juinn-Dar_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ling-Yen_Song>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming-Hung_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tung-Chieh_Kuo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASP-DAC52403.2022.9712559>
foaf:homepage <https://doi.org/10.1109/ASP-DAC52403.2022.9712559>
dc:identifier DBLP conf/aspdac/SongKWLH22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASP-DAC52403.2022.9712559 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chien-Nan_Jimmy_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juinn-Dar_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ling-Yen_Song>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming-Hung_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tung-Chieh_Kuo>
swrc:pages 80-85 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/SongKWLH22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/SongKWLH22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2022.html#SongKWLH22>
rdfs:seeAlso <https://doi.org/10.1109/ASP-DAC52403.2022.9712559>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document