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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/TakenakaKHT99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junji_Kitamichi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kenichi_Taniguchi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takashi_Takenaka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teruo_Higashino>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.1999.759989>
foaf:homepage <https://doi.org/10.1109/ASPDAC.1999.759989>
dc:identifier DBLP conf/aspdac/TakenakaKHT99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.1999.759989 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junji_Kitamichi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kenichi_Taniguchi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takashi_Takenaka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Teruo_Higashino>
swrc:pages 177-180 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/TakenakaKHT99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/TakenakaKHT99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac1999.html#TakenakaKHT99>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.1999.759989>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document