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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/WangZCHHB08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinian_Bian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhou_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xianlong_Hong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yanfeng_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yici_Cai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2008.4483977>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2008.4483977>
dc:identifier DBLP conf/aspdac/WangZCHHB08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2008.4483977 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Low power clock buffer planning methodology in F-D placement for large scale circuit design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinian_Bian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhou_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xianlong_Hong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yanfeng_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yici_Cai>
swrc:pages 370-375 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/WangZCHHB08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/WangZCHHB08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2008.html#WangZCHHB08>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2008.4483977>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:title Low power clock buffer planning methodology in F-D placement for large scale circuit design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document