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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aspdac/YangD05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hsueh-Chih_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lan-Rong_Dung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1120725.1121058>
foaf:homepage <https://doi.org/10.1145/1120725.1121058>
dc:identifier DBLP conf/aspdac/YangD05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1120725.1121058 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label On multiple-voltage high-level synthesis using algorithmic transformations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hsueh-Chih_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lan-Rong_Dung>
swrc:pages 872-876 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aspdac/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aspdac/YangD05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aspdac/YangD05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#YangD05>
rdfs:seeAlso <https://doi.org/10.1145/1120725.1121058>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aspdac>
dc:subject high-level synthesis, loop shrinking, low power circuit, multiple voltage scheduling, retiming, unfolding (xsd:string)
dc:title On multiple-voltage high-level synthesis using algorithmic transformations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document