Adaptive set pinning: managing shared caches in chip multiprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/asplos/SrikantaiahKI08
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/asplos/SrikantaiahKI08
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mahmut_T._Kandemir
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mary_Jane_Irwin
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shekhar_Srikantaiah
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1346281.1346299
>
foaf:
homepage
<
https://doi.org/10.1145/1346281.1346299
>
dc:
identifier
DBLP conf/asplos/SrikantaiahKI08
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1346281.1346299
(xsd:string)
dcterms:
issued
2008
(xsd:gYear)
rdfs:
label
Adaptive set pinning: managing shared caches in chip multiprocessors.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mahmut_T._Kandemir
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mary_Jane_Irwin
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shekhar_Srikantaiah
>
swrc:
pages
135-144
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/asplos/2008
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/asplos/SrikantaiahKI08/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/asplos/SrikantaiahKI08
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/asplos/asplos2008.html#SrikantaiahKI08
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1346281.1346299
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/asplos
>
dc:
subject
CMP, inter-processor, intra-processor, set pinning, shared cache
(xsd:string)
dc:
title
Adaptive set pinning: managing shared caches in chip multiprocessors.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document