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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/asscc/ToyamaYBSO18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Akihide_Sai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kentaro_Yoshioka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kohei_Onizuka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Koichiro_Ban>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yosuke_Toyama>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASSCC.2018.8579253>
foaf:homepage <https://doi.org/10.1109/ASSCC.2018.8579253>
dc:identifier DBLP conf/asscc/ToyamaYBSO18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASSCC.2018.8579253 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Akihide_Sai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kentaro_Yoshioka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kohei_Onizuka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Koichiro_Ban>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yosuke_Toyama>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/asscc/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/asscc/ToyamaYBSO18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/asscc/ToyamaYBSO18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/asscc/asscc2018.html#ToyamaYBSO18>
rdfs:seeAlso <https://doi.org/10.1109/ASSCC.2018.8579253>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/asscc>
dc:title A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document