MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/asscc/WatanabeDT17
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MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage.
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MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage.
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