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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/async/AcostaBVBJH95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Angel_Barriga>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Antonio_J._Acosta_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_L._Huertas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manuel_J._Bellido>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manuel_Valencia-Barrero>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ra%E2%88%9A%C4%BCl_Jim%E2%88%9A%C2%A9nez>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FWCADM.1995.514638>
foaf:homepage <https://doi.org/10.1109/WCADM.1995.514638>
dc:identifier DBLP conf/async/AcostaBVBJH95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FWCADM.1995.514638 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label New CMOS VLSI linear self-timed architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Angel_Barriga>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Antonio_J._Acosta_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_L._Huertas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manuel_J._Bellido>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manuel_Valencia-Barrero>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ra%E2%88%9A%C4%BCl_Jim%E2%88%9A%C2%A9nez>
swrc:pages 14-23 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/async/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/async/AcostaBVBJH95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/async/AcostaBVBJH95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/async/async1995.html#AcostaBVBJH95>
rdfs:seeAlso <https://doi.org/10.1109/WCADM.1995.514638>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/async>
dc:subject digital signal processing chips; VLSI; asynchronous circuits; semiconductor storage; CMOS memory circuits; CMOS VLSI linear self-timed architectures; digital signal processor circuits; self-timed techniques; synchronous VLSI circuits; hardware resources; asynchronous circuits; FIFO memories (xsd:string)
dc:title New CMOS VLSI linear self-timed architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document