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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/async/BouzafourRG0S18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aymane_Bouzafour>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hubert_Garavel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marc_Renaudin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Radu_Mateescu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wendelin_Serwe>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASYNC.2018.00021>
foaf:homepage <https://doi.org/10.1109/ASYNC.2018.00021>
dc:identifier DBLP conf/async/BouzafourRG0S18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASYNC.2018.00021 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aymane_Bouzafour>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hubert_Garavel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marc_Renaudin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Radu_Mateescu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wendelin_Serwe>
swrc:pages 34-42 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/async/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/async/BouzafourRG0S18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/async/BouzafourRG0S18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/async/async2018.html#BouzafourRG0S18>
rdfs:seeAlso <https://doi.org/10.1109/ASYNC.2018.00021>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/async>
dc:title Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document