High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/async/FerrettiOB04
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High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.
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High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells.
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