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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/async/MyersBM95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_J._Myers>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_A._Beerel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teresa_H.-Y._Meng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FWCADM.1995.514651>
foaf:homepage <https://doi.org/10.1109/WCADM.1995.514651>
dc:identifier DBLP conf/async/MyersBM95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FWCADM.1995.514651 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Technology mapping of timed circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_J._Myers>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_A._Beerel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Teresa_H.-Y._Meng>
swrc:pages 138- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/async/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/async/MyersBM95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/async/MyersBM95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/async/async1995.html#MyersBM95>
rdfs:seeAlso <https://doi.org/10.1109/WCADM.1995.514651>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/async>
dc:subject asynchronous circuits; timing; logic CAD; logic design; timed circuits; asynchronous circuits; timing information; gate library; AND gates; OR gates; C-elements; synthesis tool; ATACS (xsd:string)
dc:title Technology mapping of timed circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document