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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/async/PlosilaS97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juha_Plosila>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaisa_Sere>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASYNC.1997.587171>
foaf:homepage <https://doi.org/10.1109/ASYNC.1997.587171>
dc:identifier DBLP conf/async/PlosilaS97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASYNC.1997.587171 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Action Systems in Pipelined Processor Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juha_Plosila>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaisa_Sere>
swrc:pages 156-166 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/async/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/async/PlosilaS97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/async/PlosilaS97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/async/async1997.html#PlosilaS97>
rdfs:seeAlso <https://doi.org/10.1109/ASYNC.1997.587171>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/async>
dc:subject refinement calculus, pipelined processor design, action systems, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus (xsd:string)
dc:title Action Systems in Pipelined Processor Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document