Hierarchical gate-level verification of speed-independent circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/async/RoigCP95
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1995
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Hierarchical gate-level verification of speed-independent circuits.
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asynchronous circuits; logic testing; computational complexity; hierarchical gate-level verification; speed-independent circuits; complex gates; time complexity; state signals
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Hierarchical gate-level verification of speed-independent circuits.
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