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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/async/SeshiaBS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kenneth_S._Stevens>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Randal_E._Bryant>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjit_A._Seshia>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASYNC.2005.24>
foaf:homepage <https://doi.org/10.1109/ASYNC.2005.24>
dc:identifier DBLP conf/async/SeshiaBS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASYNC.2005.24 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Modeling and Verifying Circuits Using Generalized Relative Timing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kenneth_S._Stevens>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Randal_E._Bryant>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjit_A._Seshia>
swrc:pages 98-108 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/async/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/async/SeshiaBS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/async/SeshiaBS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/async/async2005.html#SeshiaBS05>
rdfs:seeAlso <https://doi.org/10.1109/ASYNC.2005.24>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/async>
dc:title Modeling and Verifying Circuits Using Generalized Relative Timing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document