An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/async/TiernoRRSN02
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An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz.
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FIR filter, PRML read channel, magnetic recording, asynchronous pipeline, mixed timing, dynamic logic, high-throughput, low-latency, digital arithmetic, distributed arithmetic
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An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz.
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