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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/ChakrabartiJ95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ajai_Jain>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhruva_R._Chakrabarti>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485342>
foaf:homepage <https://doi.org/10.1109/ATS.1995.485342>
dc:identifier DBLP conf/ats/ChakrabartiJ95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1995.485342 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ajai_Jain>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhruva_R._Chakrabarti>
swrc:pages 237-243 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/ChakrabartiJ95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/ChakrabartiJ95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1995.html#ChakrabartiJ95>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1995.485342>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject combinational circuits; fault diagnosis; logic testing; high level synthesis; design for testability; logic CAD; automatic test software; computational complexity; signal flow graphs; hierarchical test generation technique; combinational circuits; repetitive subcircuits; hierarchical testing algorithm; bus fault model; high-level subcircuits; high level incompatibility; state transition graph; test generation time; complete fault coverage; design for testability; ATPG (xsd:string)
dc:title An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document