Effective parallel processing techniques for the generation of test data for a logic built-in self test system.
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2000
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Effective parallel processing techniques for the generation of test data for a logic built-in self test system.
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built-in self test; logic testing; microprocessor chips; integrated circuit testing; parallel processing; logic simulation; automatic test pattern generation; logic partitioning; parallel processing; test data; logic built-in self test; complex processor; simulation time; logic simulation; random stimulus generation; signature computation; partitioning; Pseudo-Random Pattern Generators; serial compression; response data; serial pattern dependency; parallel simulation; post processing; signatures
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Effective parallel processing techniques for the generation of test data for a logic built-in self test system.
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