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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/ChenCCW16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Wen_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Harry_H._Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Po-Yao_Chuang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Simon_Y.-H._Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2016.33>
foaf:homepage <https://doi.org/10.1109/ATS.2016.33>
dc:identifier DBLP conf/ats/ChenCCW16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2016.33 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Wen_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Harry_H._Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Po-Yao_Chuang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Simon_Y.-H._Chen>
swrc:pages 197-202 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/ChenCCW16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/ChenCCW16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2016.html#ChenCCW16>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2016.33>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:title Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document