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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/Cheng00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wu-Tung_Cheng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893593>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893593>
dc:identifier DBLP conf/ats/Cheng00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893593 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wu-Tung_Cheng>
swrc:pages 10- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/Cheng00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/Cheng00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#Cheng00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893593>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject integrated circuit design; circuit CAD; automatic test pattern generation; VLSI; logic testing; built-in self test; integrated circuit economics; CAD; VLSI testing; VLSI design; embedded memories; BIST; automatic test pattern generation; ATPG; test logic; system on chip; SoC; deep Sub-Micron technologies; scan-based ATPG; test quality; test application cost; test development (xsd:string)
dc:title Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document