Testing of a parallel ternary multiplier using I2L logic.
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1995
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Testing of a parallel ternary multiplier using I2L logic.
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multivalued logic circuits; fault location; integrated injection logic; multiplying circuits; fault diagnosis; logic testing; logic design; design for testability; adders; digital arithmetic; parallel ternary multiplier; I/sup 2/L logic; generalized model; multivalued I/sup 2/L circuits; test sets; parallel multiplier; input balanced ternary full adder; precarry generator; multivalued current inputs; multivalued current outputs; generated test sets; stuck-at fault; skew fault; adder
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Testing of a parallel ternary multiplier using I2L logic.
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