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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/DoumarI00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abderrahim_Doumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hideo_Ito>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893658>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893658>
dc:identifier DBLP conf/ats/DoumarI00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893658 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Testing approach within FPGA-based fault tolerant systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abderrahim_Doumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hideo_Ito>
swrc:pages 411-416 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/DoumarI00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/DoumarI00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#DoumarI00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893658>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject field programmable gate arrays; fault tolerance; integrated circuit testing; delays; integrated logic circuits; FPGA-based fault-tolerant systems; FPGA test strategy; configurable logic blocks; user data; functional phase; test phase; on-chip configuration data shifting; shifting process control; test application; test observation; fault tolerance management logic; fault tolerance cost; testing time; chip functionality; delay overhead; Xilinx FPGA (xsd:string)
dc:title Testing approach within FPGA-based fault tolerant systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document