An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Laung-Terng_Wang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Xiaoxin_Fan>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yu_Hu_0001>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FATS.2007.61>
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dcterms:issued	2007 (xsd:gYear)
rdfs:label	An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. (xsd:string)
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swrc:pages	341-348 (xsd:string)
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dc:title	An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing. (xsd:string)
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