Test sequence compaction by reduced scan shift and retiming.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/HigamiKK95
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1995
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Test sequence compaction by reduced scan shift and retiming.
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logic testing; sequential circuits; design for testability; timing; flip-flops; logic CAD; computational complexity; test sequence compaction; reduced scan shift; retiming; full scan designed circuits; flip-flops; test length; computing time; sequential circuit; test sequence generation; transformation
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Test sequence compaction by reduced scan shift and retiming.
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