Test sequence compaction for sequential circuits with reset states.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/HigamiTK00
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Test sequence compaction for sequential circuits with reset states.
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sequential circuits; logic testing; fault simulation; signal detection; logic simulation; vectors; automatic test pattern generation; test sequence compaction; sequential circuits; reset states; test compaction method; single stuck-at fault assumption; unremovable vectors; fault-dropping fault simulation; nonfault-dropping fault simulation; test vectors; reset signal; fault detection; logic simulation; test subsequences; benchmark circuits
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Test sequence compaction for sequential circuits with reset states.
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