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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/HiraseY00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junichi_Hirase>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shinichi_Yoshimura>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893624>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893624>
dc:identifier DBLP conf/ats/HiraseY00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893624 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Faster processing for microprocessor functional ATPG. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junichi_Hirase>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shinichi_Yoshimura>
swrc:pages 191-197 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/HiraseY00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/HiraseY00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#HiraseY00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893624>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject microprocessor chips; automatic test pattern generation; instruction sets; integrated circuit testing; logic testing; identification; microprocessor functional ATPG; microprocessor tests; instruction sets; fault coverage improvement; short test pattern; processing speed increase; functional testing; test pattern generation (xsd:string)
dc:title Faster processing for microprocessor functional ATPG. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document