[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/HorngHC00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jing-Reng_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tsin-Yuan_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yea-Ling_Horng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893637>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893637>
dc:identifier DBLP conf/ats/HorngHC00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893637 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label A realistic fault model for flash memories. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jing-Reng_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tsin-Yuan_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yea-Ling_Horng>
swrc:pages 274-281 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/HorngHC00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/HorngHC00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#HorngHC00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893637>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject NAND circuits; flash memories; SPICE; fault simulation; integrated memory circuits; circuit analysis computing; fault model; flash memories; faulty behavior classification; NAND-type flash memory; SPICE models; flash cell models; circuit-level faulty behavior simulation; fault modeling; testing (xsd:string)
dc:title A realistic fault model for flash memories. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document