An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/HuangL99
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1999
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An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
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Low-power Test, Full-scan, Power Minimization, ATPG, VLSI testing
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An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
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